Current Issue : October - December Volume : 2012 Issue Number : 4 Articles : 3 Articles
HD video applications can be represented with multiple tasks consisting of tightly coupled multiple threads. Each task requires\r\nmassive computation, and their communication can be categorized as asynchronous distributed small data and large streaming\r\ndata transfers. In this paper, we propose a high performance programmable video platform that consists of four processing\r\nelement (PE) clusters. Each PE cluster runs a task in the video application with RISC cores, a hardware operating system kernel\r\n(HOSK), and task-specific accelerators. PE clusters are connected with two separate point-to-point networks: one for asynchronous\r\ndistributed controls and the other for heavy streaming data transfers among the tasks. Furthermore, we developed an application\r\nmapping framework, with which parallel executable codes can be obtained from a manually developed SystemC model of the\r\ntarget application without knowing the detailed architecture of the video platform. To show the effectivity of the platform and\r\nits mapping framework, we also present mapping results for an H.264/AVC 720p decoder/encoder and a VC-1 720p decoder with\r\n30 fps, assuming that the platform operates at 200MHz....
HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification\r\nof HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end\r\nand back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows\r\ndesigners to manipulate and integrate heterogeneous components implemented by using different hardware description languages\r\n(HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code\r\nabstraction/refinement and postrefinement verification....
In this article we present an ASIP design for a discrete fourier transform (DFT)/discrete cosine transform (DCT)/finite\r\nimpulse response filters (FIR) engine. The engine is intended for use in an accelerator-chain implementation of\r\nwireless communication systems. The engine offers a very high degree of flexibility, accepting and accelerating\r\nperformance approaches that of any-number DFT and inverse discrete fourier transform, one and two dimension\r\nDCT, and even general implementations of FIR equations. Performance approaches that of dedicated\r\nimplementations of such algorithms. A customized yet flexible redundant memory map allows processor-like\r\naccess while maintaining the pipeline full in a dedicated architecture-like manner. The engine is supported by a\r\nproprietary software tool that automatically sets the rounding pattern for the accelerator rounder to maintain a\r\nrequired signal to quantization noise or output RMS for any given algorithm. Programming of the processor is\r\ndone through a mid-level language that combines register-specific instructions with DFT/DCT/FIR specificinstructions.\r\nOverall the engine allows users to program a very wide range of applications with software-like ease,\r\nwhile delivering performance very close to hardware. This puts the engine in an excellent spot in the current\r\nwireless communications environment with its profusion of multi-mode and emerging standards...
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